Manufacturers in the electronics industry use test systems or testers to automatically test various electronic components and integrated circuits (ICs) to weed out defective devices or ICs. Broadly, there are two types of digital testers, those suitable for testing memory arrays or circuits, such as flash memory or Random Access Memories (RAM), and those suitable for testing logic circuits, such as Micro Controllers, Application Specific ICs (ASICs), and Programmable Logic Devices (PLDs). Generally, it is desirable to test ICs at several points during the manufacturing process including while they are still part of a wafer or substrate and after packaging the devices but before they are mounted or assembled on modules, cards or boards. This repetitive testing imposes demands on testers to automatically perform tests at high speed and with a high degree of accuracy. Moreover, the trend in the electronics industry has been to further increase the miniaturization of electronic devices and circuits, thereby allowing for an increase in the complexity of ICs. Thus, as ICs become more complex, the complexity of the testers must increase correspondingly.
To test the functionality of an IC, data patterns are delivered to the Device Under Test (DUT) with specific timing and voltage settings through timing generators and pin electronic channels, then data is read from the DUT with specific timing and voltage settings to ensure that the DUT responds correctly. A comparator in pin electronics channels compares the DUT output signal with an expected output signal, and couples results of the comparison back to an error capture memory.
For testing logic DUTs, data patterns are typically stored in large semiconductor memories inside the tester. For memory testing, data patterns are typically far too lengthy to store in the tester. Because of the regular array structure of a memory DUT, data patterns can be generated algorithmically using a specially built computer commonly known as an Algorithmic Pattern Generator (APG). This technique has been in practice for many years and is the industry standard method of generating memory test data patterns.
The testing of flash memory DUTs presents a unique set of challenges compared to testing of other types of memory devices. Flash memories are programmable devices that may require different programming times and voltages on each cell on each device. Since the programming is done through the Algorithmic Pattern Generator, it is currently believed that the highest throughput can be obtained when each DUT has its own APG.
Many prior art memory testers have had one APG that is fanned out to numerous timing generators and pin electronic channels to simultaneously test a number of DUTs. When flash memories are tested using this methodology, test time increases enormously because flash memories program at a very slow rate compared to their read cycle, and all DUTs must wait for the slowest DUT to finish programming before the APG can proceed. Thus, during programming the APG typically runs at a slow cycle rate decreasing the efficiency and utilization of tester resources. Dedicated conventional flash memory testers have attempted to deal with this problem by putting more APGs in the tester to give independence to each DUT.
Flash DUTs containing a small number of physical pins with many signals multiplexed onto those pins are becoming much more common. An example of such a flash DUT is a NAND flash DUT that typically has 16 pins. A more extreme example of a small pincount programmable memory is a serial EEPROM that has only 4 signal pins. Production of these DUTs is cost sensitive and can only support the use of very low cost testers. However, increasing the number of APGs in a tester to provide increased independence per DUT raises the cost of the tester prohibitively. Thus, increasing the number of APGs is not a wholly satisfactory solution.
Accordingly, there is a need for a tester and method of using the same that increases the efficiency and utilization of tester resources by maximizing use of the APG. There is a further need for a tester and method that increases the efficiency per DUT when independently testing multiple DUTs, and is also capable of testing multiple DUTs in lock step at the full cycle rate of the APG, for example during read cycle of flash DUTs.
The system and method of the present invention provides these and other advantages over the prior art.